A stack of oxide/nitride/oxide (ONO) is used as an interpolysilicon dielectric in a semiconductor device. The current method of forming the ONO stack involves first growing a thermal oxide over polysilicon. Then a nitride is deposited overlying the thermal oxide. After the nitride is deposited, either the top surface of the nitride is oxidized, or an oxide is deposited overlying the nitride. However, because devices are being scaled down due to the trend in miniaturization, the nitride layer is becoming thinner which poses the problem of nitride punch-through after successive oxidations. Furthermore, the thickness of the top oxide is limited when a nitride oxidation process is used due to the inherently slow oxidation kinetics of the nitride. Additionally, since the oxidation rate of nitride is slow and the oxidation temperature required is high, the thermal budget of the device limits the amount of oxidation that the nitride can undergo. If a thick top oxide is required, the current method uses a chemical vapor deposition (CVD) process to deposit the top oxide. However, the deposited CVD oxide is less dense than what is require& so an annealing step must be performed to densify the top oxide. This additional densification step must be performed at a high temperature, and again the thermal budget of the device constrains the mount of annealing that can be done.
The top oxide layer is important for the electrical performance of the device. However, this top oxide is exposed to a hydrofluoric acid solution (HF) during the second gate oxide formation which is detrimental to the device since the top oxide may be partially or completely removed during the etching steps.
Accordingly, a need exists for a method to form a top oxide that mimimizes the problem of nitride punch-through as well as the etching of the top oxide during HF exposure prior to second gate oxide formation.